1. Field
Exemplary embodiments of the present invention relate to a defective memory cell address storage circuit and a redundancy control circuit including the same.
2. Description of the Related Art
When a semiconductor memory device includes a few defective memory cells or even a defective memory cell, the semiconductor memory device may be discarded as a defective product. Here, to improve yields, redundancy technology may be applied by using preliminary memory cells that are previously installed in a semiconductor memory cell.
After a wafer fabrication process is completed, a defective memory cell is detected through a test, and a fuse is cut to perform a programming operation. The address information of such as a defective memory cell (that is, an address for which the fuse was cut) is stored to prepare to replace the defective memory cell with a redundancy memory cell.
FIG. 1 is a diagram of a conventional redundancy control circuit.
Referring to FIG. 1, the conventional redundancy control circuit includes a row address storage unit 110, a column address storage unit 120, a row address comparison unit 130, a column address comparison unit 140, and a redundancy control unit 150.
Hereafter, referring to FIG. 1, the operation of the conventional redundancy control circuit is described.
The row address storage unit 110 and the column address storage unit 120 include a plurality of fuses. Here, whether a fail address (e.g., an address for a defective memory cell) is actually stored among the plurality of fuses or not is stored in an enable fuse of the plurality of fuses. For example, when the enable fuse is cut, the value of the fail address is stored in the other fuses, and when the enable fuse is not cut, the value of the fail address is not stored in the other fuses. The other fuses store the respective codes of the fail address.
Hereafter, a row redundancy operation will be described.
The row address storage unit 110 is configured to store a row address corresponding to a memory cell which is to be replaced by a redundancy memory cell. Since a fail address is stored, the enable fuse is cut. Hereafter, the value stored in the row address storage unit 110 is referred to as a row fail address FRA<0:N>.
The row address storage unit 110 outputs the row fail address FRA<0:N> stored therein. Furthermore, since the enable fuse is cut, a row enable signal REN is activated.
The row address comparison unit 130 is configured to compare an address RA<0:N> inputted from outside with the row fail address FRA<0:N> and generate comparison information RCMP<0:N>. The codes of the comparison information RCMP<0:N> are activated when the codes of the inputted address RA<0:N> are identical to the codes of the row fail address FRA<0:N>, respectively. For example, when the first code RA<0> of the inputted address is identical to the first code FRA<0> of the row fail address, the first code RCMP<0> of the comparison information is activated. Therefore, when the inputted address RA<0:N> and the row fail address FRA<0:N> are completely identical to each other, all codes of the comparison information RCMP<0:N> are activated.
The redundancy control unit 150 is configured to control a row redundancy operation in response to the row enable signal REN and the comparison information RCMP<0:N>. For this operation, when both of the row enable signal REN and the comparison information RCMP<0:N> are activated, that is, when the row enable signal REN is activated and the inputted address RA<0:N> and the row fail address FRA<0:N> are identical to each other, the redundancy control unit 150 activates a row redundancy control signal RCON. The row redundancy control signal RCON is activated, a replaced redundancy word line is enabled instead of an original word line corresponding to the inputted address RA<0:N>.
A column redundancy operation may be performed in the same way as the row redundancy operation, except that an address inputted from outside is a column address CA<0:N>. When a column redundancy control signal CCON is activated, the column redundancy operation is performed.
The conventional redundancy control circuit includes a plurality of row/column address storage units 110 and 120 for storing a plurality of row/column addresses. As described above, however, the row address storage units 110 and the column address storage units 120 are controlled independently from each other. Therefore, the row address storage units 110 and the column address storage units 120 are not used interchangeably with each other. For example, it may be assumed that defective memory cell addresses are stored in all the row address storage units 110. Then, although extra column address storage units 130 remain, a defective memory cell address for a row redundancy operation may not be stored in the column address storage units 130. Therefore, the redundancy operation is less efficient.